Complementary Metal Oxide Semiconductor (CMOS) transistors developed in FinFET (Fin Field Effect Transistor) technologies generally suffer from enhanced aging degradation as compared to transistors developed in planar technologies. Digital circuit performance is degraded due to aging in two ways: (1) functional degradation, which is due to aging circuits stop performing or degrade significantly over lifetime, and (2) device failure, which is due to excessive aging that triggers an irreversible dielectric breakdown of transistors, leading to an instantaneous failure of the corresponding circuit. Due to the exponential voltage dependency of aging, digital circuits age where transistors are exposed to voltages beyond the CMOS device operating limits. One of the digital circuit topologies where internal nodes are exposed to voltages beyond the device target limit are stacked transistor configurations. In stacked transistor circuit topologies, internal nodes in the stack may see transient overshoot voltage (e.g., more than +/−10% tolerant limit). This transient overshoot may cause circuit degradation at a much faster rate than anticipated.